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  • 专利说明
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    • 专利摘要:
    In a method according to the invention for controlling a three-phase pulse rectifier system (1, 2, 3) comprising a three-phase bridge circuit (2) for exchanging power between a three-phase network (1) having a DC link capacitance (C pn) and a load converter (3) for exchanging power between the intermediate circuit capacitance (C pn) and a load, a first network phase, which currently has a highest voltage value with respect to the other network phases, connected to a positive connection point of the DC link capacitance (C pn) in temporally successive sections, a second network phase, which currently has a different voltage value with respect to the other network phases, connected to a negative terminal of the DC link capacitance (C pn), generated in a third network phase by clocking the bridge branch connected to this network phase, a sinusoidal current, and by varying the voltage of the DC link (C pn) generates a sinusoidal current in the first and the second phase of the network.
    公开号:CH714715A2
    申请号:CH00262/18
    申请日:2018-03-02
    公开日:2019-09-13
    发明作者:Walter Kolar Johann；Bortis Dominik
    申请人:Eth Zuerich；
    IPC主号:
    专利说明:

    CH 714 715 A2
    Description: The invention relates to the field of three-phase pulse rectifier systems, in particular to a method for regulating the input phase currents on sinusoidal form and the output DC voltage.
    For converting the voltage of the three-phase network into a DC voltage, active three-phase bridge circuits are generally used according to the prior art, the input terminals of which are connected to the network terminals via ballast inductances and a capacitance for supporting the DC voltage formed is arranged at the DC output thereof. By appropriate clocking of the bridge branches, which have the function of switches between the positive and the negative DC output voltage rail, an input current curve proportional to the mains voltage is then advantageously set in the sense of low mains interference and the DC output voltage is regulated to a constant value. Alternatively, an input current curve with a defined phase shift in relation to the mains voltage can also be set. However, due to the inductances arranged on the input side, this concept has a step-up converter characteristic and is therefore only suitable for the generation of DC output voltage above the peak value of the line conductor voltage. Should, such as if a battery charge of electric vehicles is required, a lower output voltage is formed, the system is to be followed by a DC / DC step-down converter stage, which results in a two-stage three-phase step-down converter pulse rectifier system with advantageously continuous, directly regulated input phase currents and continuous output current (see Fig. 1) ,
    If the step-down converter stage is executed bidirectionally, then a power supplied by an active load can also be fed into the DC link between the two converter stages, or the load voltage raised to the level of the intermediate circuit voltage and from there power can be fed back into the network. This operation is e.g. when feeding photovoltaically generated power into the three-phase network or when feeding a three-phase machine from a DC voltage.
    For a compact implementation, it is advantageous to provide a high clock frequency of the converter stages in both cases, which however results in relatively high switching losses which reduce the efficiency of the energy conversion. Furthermore, a relatively high drive power is required for the high-frequency clocking of the electronic switches, which also affects the efficiency.
    The object of the invention is therefore to provide a method for the control and modulation of a two-stage three-phase buck converter pulse rectifier system, which has reduced switching losses, with a sinusoidal, advantageously in phase or in opposite phase with the line voltage line current profile and a constant output voltage should be ensured.
    The object is achieved by a control method according to the claims.
    In the following the subject matter of the invention is explained in more detail using preferred exemplary embodiments which are illustrated in the accompanying drawings. It shows schematically:
    Fig. 1: Power section of the system, the input section being designed as a two-point bridge circuit and the load converter as a DC / DC buck converter.
    Fig. 2: Voltage profiles of the mains input voltages u a , u b and u c and the intermediate circuit voltage u pn . The subdivision into the six voltage sectors and the allocation of the line voltages to the three phases ui, u 2 and u 3 are dependent on the voltage ratios of the line input voltages.
    Fig. 3: Circuitry implementation of the method for controlling and modulating the system shown in FIG. 1.
    Fig. 4: Alternative version of the load converter as a DC / DC step-up converter.
    Fig. 5: Alternative version of the load converter as an active current-impressing series element in the form of a switch cell, i.e. the load converter is a full-bridge switch cell which is arranged in the connecting line of positive intermediate circuit voltage and positive output voltage terminal and has the function of an active smoothing or output inductance.
    Fig. 6: Alternative version of the load converter as a pulse converter, in particular as a pulse inverter, for the direct supply of a machine Μ. Without an intermediate step-down or step-up converter, at least two phases must be clocked in the inverter for regulating the machine currents; with an intermediate converter, however, the control with clamping of two phases can also be used here.
    So it is (assuming ohmic network behavior), instead of all three bridge branches in each input voltage sector only the bridge branch of the active three-phase bridge circuit clocked, which carries the smallest amount of current and in this phase, hereinafter referred to as the third phase u 3 , by Clocking of the bridge branch impressed a sinusoidal current profile. At the same time, the other two bridge branches, depending on the applied input voltage conditions or the current one (due to the size relationships of the input phase voltage
    CH 714 715 A2 through certain) input voltage sector, ie the phase with the most positive mains phase voltage instantaneous value, hereinafter referred to as first phase Ui, to the positive DC output voltage rail p and the phase with the most negative mains phase voltage instantaneous value, hereinafter referred to as second phase u 2 , clamped to the negative DC output voltage rails (see FIG. 2).
    Since pulse rectifier systems typically have no connection to the network star point m, or the sum of the phase currents is forced to zero, a defined course of all three phase currents can then be achieved by simultaneously controlling a further current. A defined profile of the intermediate circuit voltage u pn is used as the voltage for impressing the further current. Since the first phase u- is clamped to the positive DC output voltage rail p and the second phase u 2 to the negative DC output voltage rails, the intermediate circuit voltage u pn occurs in the form of a chain voltage between the inputs of the bridge branches of the first and second phases and forms, in conjunction with the associated chained voltage on the network side, a corresponding voltage which occurs across the respective series inductance L of the first and the second phase and thus impresses current (cf. FIGS. 1 and 2).
    In a departure from a conventional implementation with a time-constant intermediate circuit voltage u pn , the degree of freedom with regard to the choice of an intermediate circuit voltage curve is exploited, this being regulated in such a way that a sinusoidal current curve is also formed in the first and second phases. It should be noted here that temporal fluctuations in the intermediate circuit voltage u pn can be compensated for by corresponding pulse width modulation of the downstream step-down converter stage, ie a constant output voltage u 0 can still be formed. Since the method according to the invention avoids a clocking of the first and second phases carrying higher currents compared to the third phase, this advantageously ensures low switching losses and a low drive power requirement.
    It should be noted that the two-stage three-phase buck converter pulse rectifier system is not limited to a pure buck converter function, but can also be operated as a boost converter. In this case, the upper switch of the step-down converter on the output side must be switched through so that the output voltage u ° corresponds to the intermediate circuit voltage u pn ; the active three-phase bridge is then operated as a conventional step-up converter, with more than one bridge branch having to be clocked to regulate a constant intermediate circuit or output voltage. A method according to the prior art is then used for the control. Depending on the operation (step-down or step-up converter operation), a switch is made between the regulation according to the invention and a regulation according to the prior art.
    The to be controlled and regulated by the inventive method three-phase step-down converter pulse rectifier system is known on the input side by a three-phase two-point bridge circuit (2) or three-phase multi-point bridge circuit (bridge circuit) with three AC phase inputs (£, b and c) and a positive (p) and a negative DC output voltage rail (s), between which a buffer capacitor (intermediate circuit capacitor or intermediate circuit capacitance) (C pn ) is arranged, both DC voltage rails at the input of an output-side converter stage (load converter) (3) which feeds a consumer or generates a voltage (load voltage) (u 0 ) across the consumer (cf. FIG. 1). Furthermore, each phase input of the bridge circuit is connected via a series inductance (L) to the associated phase terminal [a, b and c) of the three-phase AC supply system (network) (1). In order to keep switching frequency components of the currents in the ballast inductances that occur during operation or to define the supply voltage independently of the internal impedance of the network, three filter capacitors (line filter capacitors) can be provided in star or delta connection on the line terminals. The bridge circuit (2) generally has three bridge branches, whereby for two-point characteristics each bridge branch has an upper electronic switch connected to the positive DC link rail (p) and a lower electronic switch connected to the negative DC link voltage rail (s), and the phase output of the bridge branch ( 2, b and ç) is formed by the connection point of the free ends of the upper and lower switch and freewheeling diodes can be connected antiparallel to the switches. For the sake of clarity, the following description is based on a two-point version of the bridge circuit.Furthermore, the load converter (3) is thought to be a simple bidirectional step-down converter, which on the input side has a two-point connected between positive (p) and negative DC voltage rail (s) - Bridge branch (step-down converter bridge branch) (31), from whose output terminal (d) a step-down converter inductance (L o ) is connected to the positive output voltage terminal (d) of the system, the negative output voltage terminal being connected directly to the negative DC voltage rail (n) and a support capacitor (output capacitor) (C o ) is arranged between the positive and the negative output terminal and the load is placed between the positive (d) and negative output terminal (s).
    The modulation of the system takes place depending on the size relationships of the line phase voltages (in other words: depending on the relations of the levels of the line phase voltages), with a first (or currently upper) line phase (u-,) a positive, a second ( or currently lower) network phase (u 2 ) has a negative and the third (or currently middle) network phase (u 3 ) has an average voltage value which at most reaches the voltage value of the first network phase (ui) and in any case above the voltage value of the second network phase (u 2 ) lies or reaches it in the borderline case. For a symmetrical three-phase network, these size relationships remain unchanged with a width of 1/6 of the network period, ie within a 60 ° wide sector or section, whereby
    CH 714 715 A2 an angle of 360 ° corresponds to a complete oscillation period of the mains voltages (cf. FIG. 2). If the size ratios change when changing to the next sector or section, the modulation is also adjusted accordingly. This means that the first, second, third (or upper, lower, middle) phase, as viewed and switched during modulation, is assigned to a different physical phase in each sector. Within a sector, the first phase (u-,) is made permanent by means of the upper switch (21) of the associated bridge branch with the positive DC voltage rail (p) and the second phase (u 2 ) is in each case by means of the lower switch (22) associated bridge branch permanently connected to the negative DC voltage rail (s) and leaving only the third phase (u 3 ) clocking with switching frequency. Switching losses thus advantageously only occur for one phase, ie the third phase (u 3 ), which have a relatively low value due to the relatively low value of the associated phase current.
    The aim of the control of the system is, in the ballast inductances (L) or in the grid phases sinusoidal, in phase (for power consumption from the grid, or in reverse phase for power recovery) with the associated grid phase voltage (u a , u b and u c ) to impress lying currents (i a , b and i c ), all currents having the same amplitude for a symmetrical network and optionally a defined load voltage (u 0 ) corresponding to a predetermined setpoint (load voltage setpoint) at the output of the load converter (3) (u 0 ) to generate, or generally to deliver a defined power to the consumer (see. Fig. 3). Alternatively, the line phase currents can also have a phase shift with respect to the associated line phase voltages. For the further description, however, ohmic network behavior is assumed for the sake of clarity. Accordingly, viewed from the grid, the system can be seen as a star connection of the same ohmic resistors (equivalent input resistances) or conductance values (equivalent input conductance values), the power of which is passed on directly to the output, ie to the consumer, with the ideal assumption of losslessness. Following this idea, the setpoint of the input equivalent conductance (input setpoint) (G *) is formed as a function of the load voltage control deviation, i.e. the difference between a specified load voltage setpoint (u 0 ') and the measured load voltage actual value (u 0 ), by feeding the load voltage control deviation to the input of an output voltage regulator which forms the required setpoint of the recharging current (ic 0 ) of the output capacitor (C o ) at the output, which, after adding the measured load current (load current pre-control) (i Loa d) and multiplying this current sum by the output reference voltage (u 0 ), sets the setpoint power to be delivered to the output (output power setpoint) (P o *) results, which is ultimately to be obtained from the network, that is, if the losses of the system are neglected, directly defines the input power setpoint. Correspondingly, in the next step, the input setpoint conductance (G *) is determined with the input phase peak value ü such that power consumption from the network results in the amount of the output power setpoint (P o ). Multiplying the input setpoint (G *) by the measured phase voltages (u a , Ub and u c ) then results in setpoints for the currents to be set in the series inductances (input phase current setpoints) (i a *, i b * and i c '). For each phase, the control deviation is determined by subtracting the measured input current actual value (i a , i b and i c ) and fed to an input current controller, which has the setpoint of the voltage to be formed across the associated series inductance (ui_ a *, Ui_b * and Ul c ) forms. After subtracting this setpoint from the measured value of the associated mains phase voltage (u a , Ub and u c ), the result is the setpoint of the input voltage of the associated bridge branch (bridge branch input voltage setpoint) (u a , and u c ) of the active bridge circuit. For the third phase (u 3 ) the bridge branch input voltage setpoint is divided by half the measured value of the intermediate circuit voltage (intermediate circuit voltage actual value) (u pn ) and thus the relative switch-on duration (d 3 ) of the upper switch of the associated bridge branch is calculated in the sense of pulse width modulation, during the switch-off period the upper switch (21) the lower switch (22) of the bridge arm is turned on, ie both switches of the bridge arm work in push-pull and the clock period preferably has a constant length or the clock frequency preferably has a constant value. Overall, the actual phase current value of the third phase is managed in accordance with the associated input phase current setpoint curve.
    A sector determination unit uses the grid phase voltages (u a , u b and u c ) to determine in which sector or section the grid phase voltages are located according to their size relationships. A modulation unit uses this sector information and the duty cycle (d 3 ) to generate switching signals S a , Sb, S c for the three bridge branches.
    Since the first phase (υ Ί ) as described above is clamped to the positive DC link voltage rail (p) and the second phase (u 2 ) to the negative DC link voltage rail ( s ) within the entire sector under consideration, for the regulation of the input current in these phases, a corresponding course of the DC link voltage (u pn ) can be used directly. The setpoint curve (υ Ί2 * = u pn ) is formed by subtracting the bridge branch input voltage setpoints of the first (ui) and the second phase (u 2 ) and the intermediate circuit voltage actual value (u pn ) is subtracted from this intermediate circuit voltage setpoint, and the intermediate circuit voltage deviation of an intermediate control is present Circuit voltage regulator supplied, at whose output the setpoint of the recharge current of the DC link capacitor (ic pn ) occurs, which after subtraction from the DC link current setpoint (i pn ) (which is calculated for each sector from the input phase setpoint current values (i a *, i b * and i c )) and after multiplication with the intermediate circuit voltage setpoint (u pn ) leads to the differential power (P pn ) which is to be removed from the intermediate circuit.
    Alternatively, the setpoint of the power to be removed from the intermediate circuit power (P pn ) can also be obtained from the subtraction of the (intermediate circuit capacitor setpoint power, by multiplying the setpoint of
    CH 714 715 A2
    Recharge current of the DC link capacitor (i c ) can be calculated with the DC link voltage setpoint (u pn ) from the input power setpoint.
    The subsequent division of the intermediate circuit setpoint power (P pn ) by the output voltage setpoint (u 0 ) leads to the setpoint of the current in the step-down converter inductance (step-down converter inductance setpoint) (i Lo ) from which the measured step-down converter inductance inductance inductance is induced ( inductance ) ,
    Alternatively, for the calculation of the current setpoint of the step-down converter inductance (ib, *) only the intermediate circuit capacitor setpoint power without setpoint input power is used, the setpoint current value (ì Lo , dc *)> which is calculated by the output voltage regulator and only a small one due to the limited bandwidth of the output voltage regulator Dynamic, can be controlled.
    The step-down converter inductance current control deviation is then applied to the input of a step-down converter current regulator, which generates at its output the voltage to be formed over the step-down converter inductance on average over a clock period (step-down converter inductance setpoint voltage) (ui_ 0 ), which after addition of the output voltage setpoint (u 0 ) output voltage (u d *) of the buck converter bridge branch required for impressing the buck converter inductance setpoint. By dividing this value by the intermediate circuit voltage setpoint (u 0 ), the relative switch-on time of the upper switch (d d ) of the step-down converter bridge branch is finally determined, the lower switch (312) being switched through within the relative switch-off time of the upper switch (311), i.e. both Switch of the bridge branch work in push-pull. In order to achieve a minimal switching-frequency fluctuation in the intermediate circuit voltage (u pn ), it is advantageous to clock the third bridge arm of the active bridge circuit and the step-down converter bridge arm with the same clock frequency and to lay the timing so that when the upper switch (21) of the third bridge arm is locked, the upper switch of the buck converter branch (311) is in the switched-through state. The intermediate circuit capacitor (C pn ) can then be designed with a relatively small capacitance, and thus the intermediate circuit voltage actual value (u pn ) can be carried out with a six-pulse curve, which is relatively small compared to the output current (i Cpn ) in accordance with the positive envelope of the mains line voltages.
    When controlling according to the preceding description, only the third phase (u 3 ) is clocked within a sector for the impression of the associated phase current , the first (υ Ί ) and the second phase (u 2 ) remain clamped. The abrupt change at the sector boundaries can lead to distortion of the phase currents (i a , i b and i c ), which is why shortly before and shortly after the sector boundary, at least one further phase can be activated and the selection of this phase takes place in such a way that Additional switching losses occur, that is to say that phase is selected whose magnitude of the phase current value is closer to the phase current value of the third phase.
    Another possibility to avoid distortions is to block the third phase for a short period of time shortly after a sector boundary (i.e. to keep all switches of the active bridge circuit locked in this period of time) and only then to release them for clocking.
    It should be noted that in addition to the design of the load converter as a DC / DC buck converter, there are several other forms of implementation:
    a DC / DC step-up converter (see FIG. 4),
    - A full bridge switch cell with internal DC voltage and series inductance, for the implementation of an active smoothing or output inductance (cf. FIG. 5). The current drawn from the DC link is here directly equal to the output current, which is impressed via appropriate clocking of the full-bridge switch cell. Since the cell only compensates for power pulsations with six times the mains frequency, no DC supply is required.
    A three-phase pulse converter, in particular a pulse inverter (see FIG. 6),
    权利要求:
    Claims (8)
    [1]
    - Or another voltage stabilizing converter stage.
    It should be noted that ohmic network behavior is assumed for the drawings, but the control method according to the invention can also be used for a phase shift of the network phase currents with respect to the assigned network phase voltages, the sector selection then still being the same and only for the phase current setpoints (which according to corresponding reactive components are added to the above statements for ohmic network behavior).
    claims
    1. A method for controlling a three-phase pulse rectifier system (1,2, 3), which has a three-phase bridge circuit (2), for power exchange between a three-phase network (1) with an intermediate circuit capacity (C pn ) and a load converter (3) for power exchange between of the intermediate circuit capacitance (C pn ) and a load, whereby bridge branches of the three-phase bridge circuit (2) each connect a network phase with either a positive or a negative connection point of the intermediate circuit capacitance (C pn ), with successive sections in each section
    a first network phase, which currently has a highest one with respect to the other network phases, is connected to a positive connection point of the intermediate circuit capacitance (C pn ),
    CH 714 715 A2
    a second network phase, which currently has a voltage value with respect to the other network phases, is connected to a negative connection point of the intermediate circuit capacitance (C pn ),
    a sinusoidal current is generated in a third network phase by clocking the bridge branch connected to this network phase,
    - A sinusoidal current is generated by varying the voltage of the intermediate circuit capacitance (C pn ) in the first and the second network phase.
    [2]
    2. The method according to claim 1, wherein in the variation of the intermediate circuit voltage (u pn ) of the intermediate circuit capacitance (C pn ) for regulating the input current in the first and the second network phase, a corresponding course of the DC is used by
    an intermediate circuit voltage setpoint (ui 2 * = u pn ) is formed by subtracting the bridge branch input voltage setpoints of the first (ui) and the second phase (u 2 ),
    subtracted from this intermediate circuit voltage setpoint (u pn ) the intermediate circuit voltage actual value (u pn ) and any intermediate circuit voltage control deviation thus present is fed to an intermediate circuit voltage regulator , at whose output a setpoint of the recharging current of the intermediate circuit capacitor (i Cpn *) occurs, and this
    - after subtraction from a DC link current setpoint (i pn *), which is calculated for each sector from input phase setpoint current values (i a *, i b * and i c ), and after multiplication by the DC link voltage setpoint (u pn ) to a differential power (P pn ) leads, which is to be removed from the intermediate circuit, and
    - By dividing the intermediate circuit setpoint power (P pn ) by the output voltage setpoint (u 0 ), a setpoint value of a current in a step-down converter inductance (step-down converter inductance setpoint) (i Lo ) of the load converter (3) is determined, and this is set by the load converter (3).
    [3]
    3. The method according to claim 1 or 2, wherein in the variation of the voltage of the intermediate circuit capacitance (C pn ) an output voltage (u 0 ) at the load and / or an output power (P o ) of the load converter (3) to the load by modulating the Load converter (3) can be regulated.
    [4]
    4. The method according to claim 1 or 2 or 3, wherein a setpoint of an input substitute conductance (input setpoint) (G *) is formed as a function of a load voltage control deviation by the load voltage control deviation is fed to the input of an output voltage regulator, which has the required setpoint of the recharging current at the output (i Co ) of the output capacitor (C o ), which, after addition of the measured load current (load current pre-control) (i Loa d) and multiplication of this current sum by the output reference voltage (u 0 '), forms a setpoint of the power to be supplied to the output (output power setpoint) (P 0 ') results and the Eingangssollleitwert is determined to (G *), that a power from the grid at the level of the output power reference value (P o) results by multiplying the Eingangssollleitwertes (G *) to the measured phase voltages (u a , u b and u c ) Setpoints to be set in the series inductors n currents (input phase current setpoints) (i a ', i b * and i c ') are determined and a control deviation is determined for each phase by subtracting a measured input current actual value (i a , i b and i c ) and fed to an input current controller which is switched on its output forms a setpoint of the voltage to be formed across the associated ballast inductance (u La *, u Lb * and Ulc), whereby after subtracting this setpoint from the measured value of the associated mains phase voltage (u a , u b and u c ) a setpoint of the input voltage of the associated bridge branch (bridge branch input voltage setpoint) (u a , u b and u c ) of the three-phase bridge circuit (2) results and is set by this.
    [5]
    5. The method according to any one of the preceding claims, wherein shortly before and shortly after a sector boundary between two sections, at least one further phase is actively switched, and the selection of this phase is carried out in such a way that reduced additional switching losses occur, that is to say that phase is selected as the switched phase whose magnitude of the phase current value is closer to the phase current value of the third phase.
    [6]
    6. The method according to any one of the preceding claims, wherein shortly after a sector boundary between two sections, the third phase is blocked for a short period of time and only then released for clocking.
    [7]
    7. The method according to any one of the preceding claims, in which the load converter (3) is a step-up converter.
    [8]
    8. The method according to any one of claims 1 to 6, in which the load converter (3) is a pulse-controlled inverter.
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    同族专利:
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    CH00262/18A|CH714715B1|2018-03-02|2018-03-02|Method for regulating a three-phase pulse rectifier system.|CH00262/18A| CH714715B1|2018-03-02|2018-03-02|Method for regulating a three-phase pulse rectifier system.|
    PCT/EP2019/055185| WO2019166642A1|2018-03-02|2019-03-01|Method for controlling a three-phase pulse rectifier system|
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